Conventionally, when data transmission is conducted between non-synchronous systems, large capacity FIFO (first-in first-out) memories are used as buffers between systems (refer to "Interface", August 1984, pp 268 to 270). For example, as shown in FIG. 1 in a case where data transmission is conducted between non-synchronously operating systems A and B, a structure is adopted in which a FIFO memory 3 is connected between the output of the system A1 and the input of the system B2, the output of the system A1 thereby being buffered. When data transmission is conducted between a plurality of non-synchronous systems, FIFO memories 8 to 10 are connected between the non-synchronous systems 4 to 7 as shown in FIG. 2.
When such FIFO memories are used for data transmission between non-synchronous systems in such a conventional data transmission apparatus, it is only possible to connect a plurality of non-synchronous systems only because FIFO memories only function to buffering data. The whole system connected by FIFO memories constitutes a pipe line processing apparatus including a simple cascade connection, which has a low degree of freedom.
The inventors have already proposed a data transmission apparatus capable of obtaining a high degree of freedom in constituting a whole system by connecting non-synchronous systems (Japanese patent applications No. Sho. 60-33035 and 60-33036). This data transmission apparatus is constituted such that an input data transmission path, an output data transmission path, a branch data transmission path, and a joining data transmission path are constructed by a non-synchronous self running shift register, whether the data on the input data transmission path is to be branched or not is judged by a branching judging means, data is given to the branch data transmission path from the input data transmission path when the data is to be branched and is given to the output data transmission path otherwise, and the data on the joining data transmission path is given to the output data transmission path when empty buffers exist in the input and output data transmission paths, whereby non-synchronous systems are capable of being connected in parallel as well as serially.
FIG. 15 shows a system of such a data transmission apparatus. In FIG. 15 the 305 designates a data transmission path, 302a to 302c designate a branching section, 303a to 303c designate a joining section, 301a to 301c designate a processing element, and 304 designates an interface.
In this system, the packet data transmitted into device through the interface 304 from an external source reaches one of the processing elements 301a to 301c circulating the network elements 303a and 302a to 302c, and is processed by the respective processing elements 301a to 301c, the processed results are collected by the network elements 303b and 303c, and sent out through the interface 304.
In the above-described data transmission apparatus, however, the branching judging means is operated by the changing from 0 to 1 of the data. In more detail, a particular bit thereof on the data transmission path is detected, thereby judging the branching condition of the data, and accordingly a case may arise where the branching judging means does not operate depending on the state of the data transmission path, particularly in such a case where the particular bit of the data directly before the start of operation triggered by the power ON is 1, and the data to be therefore cannot be branched.
Furthermore, in the above-described data transmission apparatus where a data transmission path is constituted by a self running shift register, the data is unfavourably likely to remain on the data transmission path when a device is started by the power ON function. This results in a reduced reliability.
In order to solve such a problem, the data transmission path can be initialized by resetting the self running shift registers of the data transmission path at the start of operation. This method, however, requires the resetting of all registers of the data transmission path, resulting in an increase in circuit size.
Furthermore, the above-mentioned data transmission apparatus can be applied to an arithmetic operation device, in which there may be cases where various states of function elements are to be observed. As a method of observing the observation from the flow of the data on the data transmission path can be conducted. In the above-described data transmission apparatus having the data transmission paths constituted by self running shift registers, however, the data is transmitted at a very high speed such as 25 nsec to 50 nsec, and it is impossible to observe the respective function element from the data flow.
Furthermore, when a data transmission path is constituted by a non-synchronous self running shift register, there is a request to use different kinds of C elements as transfer control circuits which give rising edge triggers to the parallel data buffers constituting the shift register. However, in this case a malfunction may occur when a control signal is input at a timing other than a predetermined one, and different kinds of C element cannot be connected as they are requested. Furthermore, a malfunction may arise in cases where C elements of the same kind but of different operation speeds are used.